Title | ||
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Fast and Accurate Exploration of Multi-level Caches Using Hierarchical Reuse Distance |
Abstract | ||
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Exploring the design space of the memory hierarchy requires the use of effective methodologies, tools, and models to evaluate different parameter values. Reuse distance is of one of the locality models used in the design exploration and permits analytical cache miss estimation, program characterization, and synthetic trace generation. Unfortunately, the reuse distance is limited to a single locality granularity. Hence, it is not a suitable model for caches with hybrid line sizes, such as sectored caches, an increasingly popular choice for large caches. In this work, we introduce a generalization to the reuse distance, which is able to capture locality seen at multiple granularities. We refer to it as Hierarchical Reuse Distance (HRD). The proposed model has same profiling and synthesis complexity as the traditional reuse distance, and our results show that HRD reduces the average miss rate error on sectored caches by more than three times. In addition, it has superior characteristics in exploring multi-level caches with conventional single line size. For instance, our method increases the accuracy on L2 and L3 by a factor of 4 and converges three orders of magnitude faster. |
Year | DOI | Venue |
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2017 | 10.1109/HPCA.2017.11 | 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA) |
Keywords | Field | DocType |
reuse distance,cache,simulation,statistical | Design space,Locality,Memory hierarchy,Computer science,Reuse,Profiling (computer programming),Parallel computing,Real-time computing,Granularity,Design exploration,Benchmark (computing) | Conference |
ISSN | ISBN | Citations |
1530-0897 | 978-1-5090-4986-8 | 2 |
PageRank | References | Authors |
0.36 | 22 | 5 |
Name | Order | Citations | PageRank |
---|---|---|---|
Rafael Kioji Vivas Maeda | 1 | 24 | 7.09 |
Qiong Cai | 2 | 133 | 7.91 |
Jiang Xu | 3 | 704 | 61.98 |
Zhe Wang | 4 | 4 | 0.76 |
Zhongyuan Tian | 5 | 7 | 3.56 |