Name
Title | ||
|---|---|---|
Area-power-efficient 11-bit hybrid dual-Vdd ADC with self-calibration for neural sensing application |
Abstract | ||
|---|---|---|
Miniaturized neural sensing microsystem has become increasingly important for brain function investigation. This paper presented a low voltage area-power-efficient 11-bit hybrid analog-to-digital convertor (ADC) with self-calibration for neural sensing application. To reduce the total amount of capacitance, the proposed hybrid ADC is composed of 3 bit coarse-tune and 8 bit fine-tune with delay-lined based ADC and successive approximation register (SAR) ADC. The three most significant bits are detected by a modified vernier structure delay-line-based ADC. Self-timed power management including dual voltage supply, power-gating and multi-threshold CMOS are employed and the capacitance mismatch due to process variation is compensated using a self-calibration scheme. The proposed 11 bit ADC is implemented in TSMC 90nm general propose (GP) CMOS technology. Post-sim results indicate that ENOB of 9.71-bits at 32KS/s sampling rate can be achieved with only 982nW power consumption and 0.026-mm
<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>
. The FOM of the proposed hybrid ADC is 36.75fJ/conversion-step. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/SOCC.2016.7905425 | 2016 29th IEEE International System-on-Chip Conference (SOCC) |
Keywords | Field | DocType |
SAR ADC,low power,self-calibration,neural sensing | Power management,Capacitance,8-bit,Effective number of bits,Electronic engineering,CMOS,Process variation,Low voltage,Successive approximation ADC,Engineering | Conference |
ISBN | Citations | PageRank |
978-1-5090-1368-5 | 0 | 0.34 |
References | Authors | |
11 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ming Chen | 1 | 581 | 85.60 |
| Po-Tsang Huang | 2 | 1 | 1.06 |
| shanglin wu | 3 | 46 | 7.90 |
| Wei Hwang | 4 | 1 | 1.74 |
| Ching-Te Chuang | 5 | 465 | 76.52 |