Name
Abstract | ||
|---|---|---|
With increased usage of compute cores for sensitive applications, including e-commerce, there is a need to provide additional hardware support for securing information from memory based attacks. This work presents a unified hardware framework for handling spatial and temporal memory attacks. The paper integrates the proposed hardware framework with a RISC-V based micro-architecture with an enhanced application binary interface that enables software layers to use these features to protect sensitive data. We demonstrate the effectiveness of the proposed scheme through practical case studies in addition to taking the design through a VLSI CAD design flow. The proposed processor reduces the metadata storage overhead up to 4 x in comparison with the existing solutions, while incurring an area overhead of just 1914 LUTs and 2197 flip flops on an FPGA, without affecting the critical path delay of the processor. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1145/3092627.3092629 | HASP@ISCA |
Field | DocType | ISBN |
RISC-V,Application binary interface,FLOPS,Computer science,Field-programmable gate array,Design flow,Abstraction layer,Tagged architecture,Buffer overflow,Embedded system | Conference | 978-1-4503-5266-6 |
Citations | PageRank | References |
2 | 0.42 | 22 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Arjun Menon | 1 | 4 | 1.14 |
| Subadra Murugan | 2 | 2 | 0.42 |
| Chester Rebeiro | 3 | 187 | 22.83 |
| Neel Gala | 4 | 9 | 3.87 |
| Kamakoti Veezhinathan | 5 | 35 | 4.04 |