Name
Title | ||
|---|---|---|
Reconfigurable Concurrent VLSI (FPGA) Design Architecture of CRC-32 for High-Speed Data Communication |
Abstract | ||
|---|---|---|
CRC (Cyclic Redundancy Check) is a simple and an elegant method for error detection. It finds application in most of the high-speed data communication protocol. In High Energy Physics experiment often CRC is used for control and data frame communication with detectors placed at radiation zone. Reliability of CRC error detection capability alters with generator polynomial chosen. The most popular choice is to use a 32-bit checksum. However, it again comes with many standards. So, in our work we have proposed a reconfigurable VLSI architecture of CRC-32 to meet the problem statement. Our approach can meet all the existing CRC-32 standards. The novelty of our design lies in the ability of CRC engine to generate checksum within a single clock cycle of information presented. The usability of our design is justified based on power, latency and resource utilization variations, with bus-width and technology changes. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/iNIS.2015.66 | INIS '15 Proceedings of the 2015 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) |
Keywords | DocType | ISBN |
Reconfigurable Logic, High Throughput En-coder, High Energy Physics, Error detection, Low latency, Power optimized, Variable bus width, CRC, checksum, FPGA | Conference | 978-1-4673-9692-9 |
Citations | PageRank | References |
0 | 0.34 | 7 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jubin Mitra | 1 | 1 | 0.72 |
| Tapan K Nayak | 2 | 21 | 3.93 |