Paper Info
Title
Software-defined board- and chip-level optical interconnects for multi-socket communication and disaggregated computing
Abstract
The vast amount of new data being generated is outpacing the development of infrastructures and continues to grow at much higher rates than MooreâĂŹs law, a problem that is commonly referred to as the âĂIJdata deluge problemâĂİ. This brings current computational machines in the struggle to exceed Exascale processing powers by 2020 and this is where the energy boundary is setting the second, bottom-side alarm: A reasonable power envelope for future Super-computers has been projected to be 20MW, while worldâĂŹs current No. 1 Supercomputer Sunway TaihuLight provides 93 Pflops and requires already 15.37 MW. This simply means that we have reached so far below 10% of the Exascale target but we consume already more than 75% of the tar-geted energy limit! The way to escape is currently following the paradigm of disaggregating and disintegrating resources, massively introducing at the same time optical technologies for interconnect purposes. Disaggregating computing from memory and storage modules can allow for flexible and modular settings where hardware requirements can be tailored to meet the certain energy and performance metrics targeted per application. At the same time, optical interconnect and photonic integration technologies are rapidly replacing electrical interconnects continuously penetrating at deeper hierarchy levels: Silicon photonics have enabled the penetration of optical technology to the computing environment, starting from rack-to-rack and gradually shifting towards board-level communications. In this article, we present our recent work towards implementing on-board single-mode optical interconnects that can support Software Defined Networking allowing for programmable and flexible computational settings that can quickly adapt to the application requirements. We present a programmable 4×4 Silicon Photonic switch that supports SDN through the use of Bloom filter (BF) labeled router ports. Our scheme significantly simplifies packet forwarding as it negates the need for large forwarding tables, supporting at the same time network size and topol-ogy changes through simple modifications in the assigned BF labels. We demonstrate 1×4 switch operation controlling the Si-Pho switch by a Stratix V FPGA board that is responsible for processing the packet ID and correlating its destination with the appropriate BF-labeled switch output port. Moving towards high-capacity board-level settings, we discuss the architecture and technology being currently promoted by the recently started H2020 project ICT-STREAMS, where single-mode optical PCBs hosting Si-based routing modules and mid-board transceiver optics expect to enable a massive any-to-any, buffer-less, collision-less and extremely low latency routing platform with 25.6Tb/s aggregate through-put. This architecture and technology are also extended to support resource disaggregation in data centers as currently being pursued in the H2020 project dREDBox, where the any-to-any collisionless routing scheme is proposed for connecting disaggregated computing and memory bricks trying to minimize remote memory access latency and energy consumption.
Year
DOI
Venue
2017
10.1145/3073763.3073776
AISTECS@HiPEAC
Field
DocType
ISBN
Supercomputer,Optical engineering,Computer science,Network packet,Real-time computing,Latency (engineering),Software-defined networking,Energy consumption,Packet forwarding,Optical interconnect,Embedded system
Conference
978-1-4503-5226-0
Citations 
PageRank 
References 
0
0.34
0
Authors
6
Name
Order
Citations
PageRank
Nikos Pleros12523.69
N. Terzenidis201.01
t alexoudi314.42
Vyrsokinos, K.403.38
G. T. Kanellos500.34
Dimitris Syrivelis612415.71