Title | ||
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A 6.6 mW 1.25-2.25 GHz low phase noise PLL frequency synthesizer based on wide tuning range Class-C VCO. |
Abstract | ||
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A wide tuning range low phase noise phase-locked loop (PLL) frequency synthesizer based on Class-C voltage-controlled oscillator (VCO) for IEEE 802.11ah is presented. Feedback loop technique is adopted to provide dynamic gate bias to the core transistors of the Class-C VCO, guaranteeing robust start-up against process, voltage and temperature (PVT) variations. Automatic frequency control (AFC) algorithm with tail bias switching scheme is proposed to guarantee start-up condition and maintain optimum oscillation amplitude across the whole tuning range, avoiding the deterioration of figure-of-merit (FoM). Implemented in 65-nm CMOS, the presented frequency synthesizer prototype achieves a tuning range of 57%, from 1.25GHz to 2.25GHz. Drawing 5.5mA current from a 1.2-V power supply, the prototype demonstrates −127.8 dBc/Hz phase noise at 1-MHz offset and −94.6 dBc/Hz in-band phase noise from a carrier of 1.536GHz. With the proposed dynamic gate bias technique and AFC-assisted tail bias switching scheme, the wide tuning range Class-C VCO exhibits a peak FoM of 187.5 dBc/Hz, with only 2.5dB variation across the whole tuning range. |
Year | DOI | Venue |
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2017 | 10.1016/j.mejo.2017.06.007 | Microelectronics Journal |
Keywords | Field | DocType |
Class-C voltage-controlled oscillator (VCO),Wide tuning range,Low phase noise,Phase-locked loop (PLL),IEEE 802.11ah,Frequency synthesizer,CMOS | Phase-locked loop,Phase noise,Frequency synthesizer,Feedback loop,Voltage-controlled oscillator,Electronic engineering,CMOS,Automatic frequency control,Engineering,dBc | Journal |
Volume | ISSN | Citations |
66 | 0026-2692 | 1 |
PageRank | References | Authors |
0.35 | 7 | 4 |
Name | Order | Citations | PageRank |
---|---|---|---|
Jianfu Lin | 1 | 5 | 1.45 |
Zheng Song | 2 | 9 | 3.27 |
Wei Meng | 3 | 294 | 30.14 |
Baoyong Chi | 4 | 184 | 51.00 |