Name
Abstract | ||
|---|---|---|
In this study, the authors introduce MIPSfpga and its accompanying set of learning materials. MIPSfpga is a teaching infrastructure that offers access to the non-obfuscated Register-Transfer Level (RTL) source code of the MIPS microAptiv UP processor. The core is made available by Imagination Technologies for academic use and is targeted to a field-programmable gate array (FPGA), making it ideal f... |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1049/iet-cds.2016.0383 | IET Circuits, Devices & Systems |
Keywords | Field | DocType |
computer architecture,computer science education,electronic engineering education,field programmable gate arrays,hardware-software codesign,learning (artificial intelligence),microprocessor chips,source code (software),system-on-chip | Computer architecture,System on a chip,Cache,Source code,Field-programmable gate array,Software,Content management,Mathematics,Debugging,Microarchitecture,Embedded system | Journal |
Volume | Issue | ISSN |
11 | 4 | 1751-858X |
Citations | PageRank | References |
0 | 0.34 | 4 |
Authors | ||
8 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sarah Harris | 1 | 1 | 1.02 |
| David Money Harris | 2 | 56 | 6.20 |
| Daniel Chaver | 3 | 117 | 11.35 |
| Robert Owen | 4 | 0 | 0.68 |
| Zubair L. Kakakhel | 5 | 0 | 0.34 |
| Enrique Sedano | 6 | 0 | 0.34 |
| Yuri Panchul | 7 | 0 | 0.34 |
| Bruce Ableidinger | 8 | 0 | 0.34 |