Name
Abstract | ||
|---|---|---|
This brief proposes a low-power low-density parity check convolutional code (LDPC-CC) decoder that is fully compatible with the IEEE 1901 standard. The proposed architecture merges multiple memory banks into one to make it consume much less power than the conventional architecture. Memory operations conducted by all the unit processors are synchronized in the proposed decoder to merge the memory a... |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/TCSII.2016.2638472 | IEEE Transactions on Circuits and Systems II: Express Briefs |
Keywords | Field | DocType |
Program processors,Decoding,Hazards,Standards,Iterative decoding,Memory management,Memory architecture | Memory bank,Interleaved memory,Uniform memory access,Computer science,Distributed memory,Memory management,Memory address,Flat memory model,Computer hardware,Memory architecture | Journal |
Volume | Issue | ISSN |
64 | 9 | 1549-7747 |
Citations | PageRank | References |
1 | 0.37 | 9 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Injae Yoo | 1 | 27 | 5.26 |
| In-Cheol Park | 2 | 888 | 124.36 |