Name
Title | ||
|---|---|---|
A Spatial and Temporal Locality-Aware Adaptive Cache Design With Network Optimization for Tiled Many-Core Architectures. |
Abstract | ||
|---|---|---|
The spatial locality and the temporal locality of workloads are the root causes for cache designs to overcome the memory wall problem. However, the real memory access behavior for each of these applications can be very different. It gives the opportunities to explore further performance improvement due to different cache organization requirements. To address this issue, a spatial and temporal loca... |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/TVLSI.2017.2712366 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Keywords | Field | DocType |
Prefetching,Optimization,Adaptive systems,Organizations,Runtime,Network-on-chip,Interference | Cache-oblivious algorithm,Cache invalidation,Locality of reference,Cache pollution,Computer science,Cache,Parallel computing,Real-time computing,Cache algorithms,Cache coloring,Instruction prefetch | Journal |
Volume | Issue | ISSN |
25 | 9 | 1063-8210 |
Citations | PageRank | References |
0 | 0.34 | 30 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mingyu Wang | 1 | 135 | 24.90 |
| Zhaolin Li | 2 | 28 | 9.06 |