Name
Abstract | ||
|---|---|---|
Test points are inserted into integrated circuits to increase fault coverage especially in logic built-in self-test schemes. Commercial tools have been developed over the past decade to insert test points in circuits under test, but they are often inefficient and incur unacceptably large area overhead. Our analysis shows that many test points have little or no impact on test coverage. Furthermore,... |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/TVLSI.2017.2704104 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Keywords | Field | DocType |
Timing,Circuit faults,Tools,Optimization,Built-in self-test,Estimation | Code coverage,Automatic test pattern generation,Fault coverage,Computer science,Electronic circuit,Test compression,Integrated circuit,Reliability engineering,Test point insertion,Built-in self-test | Journal |
Volume | Issue | ISSN |
25 | 9 | 1063-8210 |
Citations | PageRank | References |
1 | 0.34 | 24 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Miao He | 1 | 16 | 5.48 |
| Gustavo K. Contreras | 2 | 21 | 2.81 |
| Dat Tran | 3 | 454 | 78.64 |
| LeRoy Winemberg | 4 | 75 | 11.09 |
| Mohammad Tehranipoor | 5 | 3181 | 243.40 |