Paper Info
Title
Analysis of reversion losses in charge pumps and its impact on efficiency for low power design
Abstract
Reversion losses are a major cause in degrading the efficiency of charge pumps (CPs) and a non-overlapping clock scheme is crucial to eliminate these losses and improve the CP's efficiency. However, employing a non-overlapping clock scheme will increase the total Silicon area and can increase the total current consumption of the CP. The increase in CP's current consumption, due to a non-overlap clock scheme, is dependent on the scheme's current consumption and on the improvement in efficiency it provides. The latter depends on the severity of reversion losses' impact on the CP's efficiency and output voltage for a set of design parameters. This paper analyzes reversion losses in cross-coupled CPs and characterizes them with a mathematical model. The model can be used by designers to evaluate the impact of reversion losses on the CP's efficiency and accordingly assess the merit of using a non-overlapping clock scheme for different design parameters. The model is verified through circuit simulations in Cadence environment using a CMOS 0.18μm 6-metal layers technology.
Year
DOI
Venue
2017
10.1109/NEWCAS.2017.8010092
2017 15th IEEE International New Circuits and Systems Conference (NEWCAS)
Keywords
Field
DocType
reversion losses analysis,charge pumps,low power design,nonoverlapping clock scheme,CP efficiency,silicon area,current consumption,cross-coupled CPs,mathematical model,circuit simulations,Cadence environment,CMOS 6-metal layers technology,size 0.18 mum
Cadence,Capacitor,Computer science,Semiconductor device modeling,Voltage,Electronic engineering,CMOS,Current consumption
Conference
ISSN
ISBN
Citations 
2472-467X
978-1-5090-4992-9
1
PageRank 
References 
Authors
0.35
5
2
Name
Order
Citations
PageRank
Majd H. Eid110.35
E Rodriguez-Villegas210319.22