Paper Info
Title
A High-Speed and SPA-Resistant Implementation of ECC Point Multiplication Over GF(p)
Abstract
In this paper, we propose a novel high-speed and SPA-resistant architecture for elliptic curve cryptography (ECC) point multiplication. A new Karatsuba-Ofman based pipelined multiplier is proposed to lower the latency, and an improved comb point multiplication method is employed to reduce the clock cycles and to resist simple power analysis (SPA). The proposed ECC architecture has been implemented on Altera's Stratix II FPGA platform. Implementation results show that our processor can perform 256-bit ECC point multiplication in 0.16 ms at the cost of 14.2k ALMs. Compared with the previous implementations, our implementation achieves a speed up factor of no less than 4 times without compromising the SPA-resistance.
Year
DOI
Venue
2017
10.1109/Trustcom/BigDataSE/ICESS.2017.245
2017 IEEE Trustcom/BigDataSE/ICESS
Keywords
Field
DocType
Elliptic curve cryptography (ECC),Karatsuba-Ofman,comb point multiplication,SPA-resistant
Power analysis,Stratix,Computer science,Latency (engineering),Parallel computing,Field-programmable gate array,Multiplier (economics),Multiplication,Elliptic curve cryptography,Speedup
Conference
ISSN
ISBN
Citations 
2324-9013
978-1-5090-4907-3
0
PageRank 
References 
Authors
0.34
6
2
Name
Order
Citations
PageRank
Xiang Feng1369.16
Shuguo Li24415.97