Paper Info
Title
A power minimized 74 fJ/conversion-step 88.6 dB SNR incremental ΣΔ ADC with an asynchronous SAR quantizer
Abstract
Incremental analog to digital converters (lADCs) are aimed at converting low frequency signals with high accuracy. However the use of high oversampling ratios (OSR) usually decreases the conversion speed making them energy inefficient. The first integrator also consumes a lot of power due to high settling requirements, if a single bit quantizer is used. This paper introduces a two step feedforward IADC using an asynchronous Successive Approximation Register (SAR) ADC as a multi-bit quantizer. The same SAR ADC is then used to convert the residue of the incremental conversion. The extended counting enables high conversion speed and the use of a multibit quantizer reduces settling requirements for the first integrator. As a result, high power efficiency is achieved. The ADC achieves a peak SNR of 88.6 dB within a Nyquist bandwidth of 2.5 kHz, with a power consumption of only 8.44 μW. The measured Waiden and Schreier FoMs are 74 fj/conv.-step and 173.3 dB, respectively.
Year
DOI
Venue
2017
10.1109/ISCAS.2017.8050248
2017 IEEE International Symposium on Circuits and Systems (ISCAS)
Keywords
Field
DocType
SNR,ΣΔ ADC,asynchronous SAR quantizer,analog to digital converters,integrator,asynchronous successive approximation register ADC,multi-bit quantizer,Nyquist bandwidth,power consumption,Waiden,Schreier,FoM,energy 74 fJ,bandwidth 2.5 kHz,power 8.44 muW
Electrical efficiency,Oversampling,Computer science,Control theory,Nyquist frequency,Integrator,Electronic engineering,Bandwidth (signal processing),Successive approximation ADC,Quantization (signal processing),Feed forward
Conference
ISBN
Citations 
PageRank 
978-1-5090-1427-9
1
0.36
References 
Authors
5
4
Name
Order
Citations
PageRank
saqib mohamad123.18
Chao Wu2158.86
George Jie Yuan317422.14
Amine Bermak449390.25