Name
Abstract | ||
|---|---|---|
In this paper, we propose a 1-bit Full Adder circuit built with Ballistic Deflection Transistors (BDT). BDT is a disruptive technology based on AlGaAs/InGaAs heterostructure. Different combinational circuits were successfully realized using BDT NAND gate and General Purpose Gate (GPG) structures. The developed circuit is an extension of BDT GPG and different from that of the previously implemented adder circuit. The proposed Adder consists of Sum and Carryout structures, comprising seven and five BDTs, respectively. Monte Carlo modeling of a BDT NAND Gate, which consists of associating two BDTs, has been performed and the obtained I-V characteristics were integrated with Verilog AMS to investigate the feasibility of the proposed circuit. Simulation results performed on Cadence Spectre simulator indicate the correct functionality of the proposed full adder. |
Year | Venue | Keywords |
|---|---|---|
2017 | 2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | Ballistic Devices, Ballistic Deflection Transistor, Monte Carlo Simulations, Verilog AMS, Full Adder, Logic Low, Logic High |
Field | DocType | ISSN |
Logic gate,Monte Carlo method,Adder,Computer science,Verilog-AMS,Electronic engineering,NAND gate,Combinational logic,Resistor,Transistor,Electrical engineering | Conference | 0271-4302 |
Citations | PageRank | References |
0 | 0.34 | 1 |
Authors | ||
8 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Poorna Marthi | 1 | 0 | 1.01 |
| Nazir Hossain | 2 | 0 | 1.01 |
| Huan Wang | 3 | 0 | 0.68 |
| Jean-François Millithaler | 4 | 0 | 1.69 |
| Martin Margala | 5 | 318 | 55.78 |
| Ignacio Iñiguez-de-la-Torre | 6 | 0 | 0.68 |
| Javier Mateos | 7 | 0 | 0.34 |
| T. González | 8 | 0 | 1.35 |