Name
Abstract | ||
|---|---|---|
This paper presents a fine-coarse time interval measurement scheme which is resilient to the variations of process, voltage, and temperature (PVT). Two Delay Locked Loops (DLLs) have been utilized to minimize the effects of PVT on the measured time intervals. A two-step time-to-digital converter is designed to ensure a high-resolution measurement over a wide dynamic range. The proposed scheme has been implemented using CMOS 65nm technology. Simulation results using ADS tools indicate that the measurement resolution varies by less than 0.12ps with +/- 15% variations of power supply voltage. The proposed method also presents a robust performance against process and temperature variations. The measurement resolution changes by few femtoseconds from slow to fast corners for process variations and it varies by a maximum of 0.1ps with changes from -40 degrees C to + 100 degrees C in temperature. |
Year | Venue | Keywords |
|---|---|---|
2017 | 2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | PVT resistant, high-resolution time interval measurement, time-to-digital converter (TDC), Vernier TDC |
Field | DocType | ISSN |
Wide dynamic range,Dynamic range,Propagation delay,Computer science,Voltage,Electronic engineering,CMOS,Time-to-digital converter,Temperature measurement | Conference | 0271-4302 |
Citations | PageRank | References |
1 | 0.36 | 6 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Esrafil Jedari | 1 | 42 | 5.81 |
| Rashid Rashidzadeh | 2 | 92 | 15.98 |
| Mehrdad Saif | 3 | 334 | 48.75 |