Title
A High-Speed Level Shifting Technique And Its Application In High-Voltage, Synchronous Dc-Dc Converters With Quasi-Zvs
Abstract
This paper presents a level-shifting technique for high-voltage power converter applications. The proposed circuit effectively combines capacitive and active coupling of the input low (high) side signal to the output high (low) side to reduce the propagation delay of the level-shifting operation. By using the resulting circuit, (i) the high-side PMOS switch is driven at high speed and (ii) a quasi-zero voltage switching (ZVS) of the low side NMOS switch is achieved. The circuit has been designed and simulated at the transistor level using a 0.18-mu m BCD process. At the high-side, remarkable simulated average level-shifter propagation delay and total driving delay have been achieved: 0.5 ns and 1.9 ns, respectively. The proposed level-shifter consumes 48.5 mu A of average current.
Year
Venue
Field
2017
2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)
Logic gate,NMOS logic,Propagation delay,Computer science,Voltage,Electronic engineering,Capacitive sensing,Converters,Transistor,High voltage,Electrical engineering
DocType
ISSN
Citations 
Conference
0271-4302
0
PageRank 
References 
Authors
0.34
3
6
Name
Order
Citations
PageRank
A. Salimath100.34
G. Gonano200.34
Edoardo Bonizzoni316247.30
D. L. Brambilla400.34
Edoardo Botti5122.08
Franco Maloberti6686144.70