Name
Title | ||
|---|---|---|
Comprehensive Performance And Robustness Analysis Of 2d Turn Models For Network-On-Chips |
Abstract | ||
|---|---|---|
Routing algorithms play an important role in Network-on-Chip (NoC) based System-on-Chips. Turn model based routing disallows some of the turns in order to avoid deadlock, while providing partial adaptivity. In this paper, all 2D uniform turn models are examined for deadlock freeness and connectivity; 50 deadlock free turn models are extracted that provide full connectivity in the network. An extended adaptivity metric is introduced to classify the turn models; all extracted turn models are compared in terms of adaptivity, robustness and latency. Experimental results identify the most robust turn models and the most efficient ones in terms of latency. |
Year | Venue | Keywords |
|---|---|---|
2017 | 2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | Turn Model, Routing Algorithm, Robustness, Minimal Path, Network-on-Chip |
Field | DocType | ISSN |
Network on,Deadlock free,Computer science,Latency (engineering),System recovery,Deadlock,Robustness (computer science),Distributed computing,Routing algorithm | Conference | 0271-4302 |
Citations | PageRank | References |
0 | 0.34 | 7 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Siavoosh Payandeh Azad | 1 | 11 | 6.94 |
| Behrad Niazmand | 2 | 22 | 5.76 |
| Karl Janson | 3 | 4 | 1.55 |
| Thilo Kogge | 4 | 0 | 0.34 |
| Jaan Raik | 5 | 211 | 51.77 |
| Gert Jervan | 6 | 73 | 13.53 |
| Thomas Hollstein | 7 | 0 | 1.01 |