Paper Info
Title
A hardware-friendly hierarchical HEVC motion estimation algorithm for UHD applications
Abstract
High Efficiency Video Coding (HEVC) standard has a superior video compression rate compared with previous H.264/AVC. At the same time, Ultra-high-definition (UHD) video applications are becoming a reality under the development of the display technology. In this paper, a hardware-friendly multi-layer HEVC motion estimation (ME) algorithm for UHD applications are proposed. To keep the computational regularity of the traditional full-search (FS) ME algorithm as well as reduce the computational complexity of ME in a large search range (SR), the basic layer of the proposed algorithm is to combine FS scheme in a core area with downsampling search scheme in a large peripheral area. Moreover, the finer layer of the algorithm employs a hexagon search scheme to perform further ME around the optimal match point generated by the basic layer. Integrating the proposed algorithm into the HM 15.0, experimental results show that our hardware-friendly algorithm can achieve 97.8% of computations reduction while only 0.77% of BD-rate loss on average. Consequently, the proposed algorithm is feasible for HEVC ME hardware design for UHD applications.
Year
DOI
Venue
2017
10.1109/ISCAS.2017.8050322
2017 IEEE International Symposium on Circuits and Systems (ISCAS)
Keywords
Field
DocType
Motion Estimation,HEVC,UHD,Hardware-Friendly,Algorithm
Algorithm design,Quarter-pixel motion,Computer science,Motion estimation,Data compression,Upsampling,Computer hardware,Computation,Computational complexity theory,Encoding (memory)
Conference
ISSN
ISBN
Citations 
0271-4302
978-1-5090-1427-9
0
PageRank 
References 
Authors
0.34
4
4
Name
Order
Citations
PageRank
Li Hu100.34
Jiawei Gu210.72
Guanghui He303.04
Weifeng He46114.69