Paper Info
Title
High performance binary neural networks on the Xeon+FPGA™ platform
Abstract
Convolutional neural networks (CNNs) are deployed in a wide range of image recognition, scene segmentation and object detection applications. Achieving state of the art accuracy in CNNs often results in large models and complex topologies that require significant compute resources to complete in a timely manner. Binarised neural networks (BNNs) have been proposed as an optimised variant of CNNs, which constrain the weights and activations to +1 or -1 and thus offer compact models and lower computational complexity per operation. This paper presents a high performance BNN accelerator on the Intel®Xeon+FPGA™ platform. The proposed accelerator is designed to take advantage of the Xeon+FPGA system in a way that a specialised FPGA architecture can be targeted for the most compute intensive parts of the BNN whilst other parts of the topology can be handled by the Xeon™ CPU. The implementation is evaluated by comparing the raw compute performance and energy efficiency for key layers in standard CNN topologies against an Nvidia Titan X Pascal GPU and other published FPGA BNN accelerators. The results show that our single-package integrated Arria™ 10 FPGA accelerator coupled with a high-end Xeon CPU can offer comparable performance and better energy efficiency than a high-end discrete Titan X GPU card. In addition, our solution delivers the best performance compared to previous BNN FPGA implementations.
Year
DOI
Venue
2017
10.23919/FPL.2017.8056823
2017 27th International Conference on Field Programmable Logic and Applications (FPL)
Keywords
Field
DocType
high performance binary neural networks,convolutional neural networks,CNN,Xeon CPU,Intel Xeon+FPGA platform,FPGA BNN accelerators,Nvidia Titan X Pascal GPU,specialised FPGA architecture,Xeon+FPGA system,high performance BNN accelerator,lower computational complexity,complex topologies,object detection applications,scene segmentation,image recognition
Object detection,Computer science,Convolutional neural network,Efficient energy use,Parallel computing,Field-programmable gate array,Network topology,Real-time computing,Xeon,Artificial neural network,Computational complexity theory
Conference
ISBN
Citations 
PageRank 
978-1-5386-2040-3
11
0.87
References 
Authors
7
7
Name
Order
Citations
PageRank
Duncan J. M. Moss1917.74
Eriko Nurvitadhi239933.08
Jaewoong Sim338417.25
Asit K. Mishra4121646.21
Debbie Marr517512.39
Suchit Subhaschandra6825.50
Philip H.W. Leong7849101.45