Name
Abstract | ||
|---|---|---|
Field Programmable Gate Array (FPGA) has been widely adopted as modern reconfigurable computing platforms. Traditionally, the storage elements in FPGAs are static RAM (SRAM), which has large leakage power and limited scalability. Recently, non-volatile memory (NVM) is proposed to replace the SRAM in FPGA systems for static power and density considerations, at the cost of inducing larger dynamic power. Hybrid FPGAs combine the advantages of SRAM and NVM by employing both SRAM and NVM as logic storage elements. Although the feasibility of hybrid FPGA has been confirmed, the design flow has not fully explored the hybrid features yet, resulting in inferior system performance. Besides, traditional design flow does not consider the reconfiguration cost, which may prolong the reconfiguration procedures and thus degrade the system performance in dynamically reconfigurable FPGA systems. This work proposes a runtime and reconfiguration dual aware placement strategy for dynamically reconfigurable hybrid architecture. The proposed scheme considers the tradeoff between runtime and dynamic reconfiguration latency and optimizes the overall performance of the reconfigurable system. Evaluation shows that the proposed scheme improves the system performance by 14.6% for SRAM-MRAM hybrid FPGAs compared with the default placement strategy. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/NVMSA.2017.8064477 | 2017 IEEE 6th Non-Volatile Memory Systems and Applications Symposium (NVMSA) |
Keywords | Field | DocType |
reconfiguration dual-aware placement,SRAM-NVM hybrid FPGAs,Field Programmable Gate Array,static RAM,leakage power,nonvolatile memory,static power,density considerations,logic storage elements,reconfiguration cost,dynamically reconfigurable FPGA systems,reconfiguration dual aware placement strategy,dynamically reconfigurable hybrid architecture,SRAM-MRAM hybrid FPGAs,default placement strategy,design flow,runtime dual-aware placement,reconfigurable computing platforms,system performance degradation,dynamic reconfiguration latency | Field-programmable gate array,Static random-access memory,Design flow,Dynamic demand,Non-volatile memory,Engineering,Control reconfiguration,Scalability,Reconfigurable computing,Embedded system | Conference |
ISSN | ISBN | Citations |
2575-2561 | 978-1-5386-1769-4 | 1 |
PageRank | References | Authors |
0.35 | 10 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Qian Lou | 1 | 5 | 4.42 |
| mengying zhao | 2 | 104 | 14.44 |
| Lei Ju | 3 | 265 | 29.03 |
| Chun Jason Xue | 4 | 1616 | 140.95 |
| Jingtong Hu | 5 | 963 | 76.16 |
| zhiping jia | 6 | 463 | 60.64 |