Name
Title | ||
|---|---|---|
DeftNN: addressing bottlenecks for DNN execution on GPUs via synapse vector elimination and near-compute data fission. |
Abstract | ||
|---|---|---|
Deep neural networks (DNNs) are key computational building blocks for emerging classes of web services that interact in real time with users via voice, images and video inputs. Although GPUs have gained popularity as a key accelerator platform for deep learning workloads, the increasing demand for DNN computation leaves a significant gap between the compute capabilities of GPU-enabled datacenters and the compute needed to service demand.
The state-of-the-art techniques to improve DNN performance have significant limitations in bridging the gap on real systems. Current network pruning techniques remove computation, but the resulting networks map poorly to GPU architectures, yielding no performance benefit or even slowdowns. Meanwhile, current bandwidth optimization techniques focus on reducing off-chip bandwidth while overlooking on-chip bandwidth, a key DNN bottleneck.
To address these limitations, this work introduces DeftNN, a GPU DNN execution framework that targets the key architectural bottlenecks of DNNs on GPUs to automatically and transparently improve execution performance. DeftNN is composed of two novel optimization techniques - (1) synapse vector elimination, a technique that identifies non-contributing synapses in the DNN and carefully transforms data and removes the computation and data movement of these synapses while fully utilizing the GPU to improve performance, and (2) near-compute data fission, a mechanism for scaling down the on-chip data movement requirements within DNN computations. Our evaluation of DeftNN spans 6 state-of-the-art DNNs. By applying both optimizations in concert, DeftNN is able to achieve an average speedup of 2.1X on real GPU hardware. We also introduce a small additional hardware unit per GPU core to facilitate efficient data fission operations, increasing the speedup achieved by DeftNN to 2.6X.
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Year | DOI | Venue |
|---|---|---|
2017 | 10.1145/3123939.3123970 | MICRO-50: The 50th Annual IEEE/ACM International Symposium on Microarchitecture
Cambridge
Massachusetts
October, 2017 |
Keywords | Field | DocType |
GPU Architecture, Deep Neural Networks, Memory Bandwidth, Performance Optimization | Bottleneck,Computing Methodologies,Memory bandwidth,Computer science,Parallel computing,Real-time computing,Bandwidth (signal processing),Artificial intelligence,Deep learning,Web service,Computation,Speedup | Conference |
ISSN | ISBN | Citations |
1072-4451 | 978-1-4503-4952-9 | 18 |
PageRank | References | Authors |
0.65 | 43 | 9 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Parker Hill | 1 | 39 | 2.70 |
| Animesh Jain | 2 | 23 | 1.06 |
| Mason Hill | 3 | 18 | 0.65 |
| Babak Zamirai | 4 | 58 | 3.64 |
| Chang-Hong Hsu | 5 | 154 | 6.69 |
| Michael A. Laurenzano | 6 | 467 | 21.23 |
| Scott Mahlke | 7 | 4811 | 312.08 |
| Lingjia Tang | 8 | 1229 | 46.41 |
| Jason Mars | 9 | 61 | 3.98 |