Name
Title | ||
|---|---|---|
A combination of a digital foreground and background calibration for a 16 bit and 200MS/s pipeline analog-to-digital converter. |
Abstract | ||
|---|---|---|
High-Performance Analog-to-Digital Converter (ADC) have high requirements concerning sampling rate and linearity. Therefore a new formula is derived to determine, which pipeline stage dependent on the used capacitor sizes needs to be calibrated for the targeted linearity. Furthermore, a model of a 16 bit and 200 MS/s pipeline ADC is described. A combination of a digital foreground and a digital background calibration is presented, which can compensate linear errors and achieves a DNL smaller than ±1 and a THD of −88 dB. |
Year | Venue | Field |
|---|---|---|
2017 | ECCTD | Pipeline transport,Total harmonic distortion,Computer science,16-bit,Linearity,Sampling (signal processing),Electronic engineering,Analog-to-digital converter,Successive approximation ADC,Calibration |
DocType | Citations | PageRank |
Conference | 0 | 0.34 |
References | Authors | |
1 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Robert Loehr | 1 | 0 | 1.01 |
| Markus Stadelmayer | 2 | 0 | 0.68 |
| Juergen Roeber | 3 | 2 | 3.07 |
| Frank Ohnhaeuser | 4 | 0 | 0.34 |
| robert weigel | 5 | 88 | 44.83 |