Name
Abstract | ||
|---|---|---|
Recently, Phase Change Memory (PCM), one of non-volatile memory (NVM), has provided a great chance to improve the performance of memory subsystem. In this paper, we propose a novel page caching policy for PCM and DRAM hybrid memory architecture called CLOCK-HM (CLOCK for page cache in Hybrid Memory architecture). Through two lists and some flag bits, it tries to minimize the write access occurrences on PCM and the migrations between DRAM and PCM, while maintaining a high page hit ratio. Simulation results show that CLOCK-HM maintains a high hit ratio as similar as CLOCK algorithm. Importantly, compared to other algorithms, CLOCK-HM significantly reduces the number of write operations on PCM and the migrations between PCM and DRAM. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/ICESS.2016.17 | 2016 13th International Conference on Embedded Software and Systems (ICESS) |
Keywords | Field | DocType |
DRAM,PCM,Hybrid Memory architecture,CLOCK-HM,Page caching | Dram,Registered memory,Phase-change memory,Computer science,Hit ratio,Page cache,Memory architecture,Memory rank,Embedded system | Conference |
ISSN | ISBN | Citations |
2576-3504 | 978-1-5090-3728-5 | 0 |
PageRank | References | Authors |
0.34 | 8 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Cai Xiaojun | 1 | 19 | 4.14 |
| Lei Ju | 2 | 265 | 29.03 |
| mengying zhao | 3 | 104 | 14.44 |
| Zhiwen Sun | 4 | 3 | 1.05 |
| zhiping jia | 5 | 463 | 60.64 |