Name
Title | ||
|---|---|---|
OCEAN: An on-chip incremental-learning enhanced processor with gated recurrent neural network accelerators. |
Abstract | ||
|---|---|---|
A deep learning processor with 8 gated recurrent neural network (RNN) accelerators is proposed in this paper. It features on-chip incremental learning by numerical and local gradient computation enhancement. Extra precision of training is obtained without extending the bit-width. Tri-mode weight access (DMA/FIFO/RAM) improves the throughput during incremental learning. The number multipliers and activation function engines are reduced by hardware sharing. The processor is fabricated in 65nm CMOS, consumes 155mW at 400MHz /1.2V or 6.6mW at 20MHz /0.8V. It achieves a peak throughput of 54.2Kfps and energy efficiency of 0.24 mu J/classification on MNIST. Demonstrations are accomplished on sequential AI tasks such as text-based motion detection and real-time wake-up word speech recognition. |
Year | Venue | Field |
|---|---|---|
2017 | ESSCIRC 2017 - 43RD IEEE EUROPEAN SOLID STATE CIRCUITS CONFERENCE | System on a chip,MNIST database,Motion detection,FIFO (computing and electronics),Computer science,Recurrent neural network,CMOS,Electronic engineering,Artificial intelligence,Throughput,Deep learning |
DocType | Citations | PageRank |
Conference | 0 | 0.34 |
References | Authors | |
5 | 11 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chixiao Chen | 1 | 6 | 4.36 |
| Hongwei Ding | 2 | 181 | 31.78 |
| Huwan Peng | 3 | 3 | 1.40 |
| Haozhe Zhu | 4 | 4 | 2.76 |
| Rui Ma | 5 | 0 | 0.34 |
| Peiyong Zhang | 6 | 0 | 0.68 |
| Xiaolang Yan | 7 | 129 | 25.85 |
| Yu Wang | 8 | 0 | 0.34 |
| Mingyu Wang | 9 | 135 | 24.90 |
| Hao Min | 10 | 26 | 9.26 |
| C.-J. Richard Shi | 11 | 491 | 61.35 |