Title
Analysis and Design of Single Reference Reduced Summer Loading-Based Switched Capacitor DFE.
Abstract
Decision feedback equalizers (DFE) are an integral part of modern serial link receivers. Attenuation in wireline communication channels causes pulse spreading. Hence, multi-tap post-cursor cancellation is necessary for reliable recovery of data at the receiver. However, the addition of multiple taps causes loading on the analog summing node which degrades the bandwidth of operation. This paper explores the design parameters of a switched capacitor-based DFE for multi-tap post-cursor cancellation with reduced summer loading. The architecture is validated by post-layout simulations done in UMC65SP technology. A PRBS-7 generator is used, and test cases are simulated upto 4.0 Gbps for two different channel attenuations around 20 dB.
Year
DOI
Venue
2017
10.1007/s00034-017-0664-9
CSSP
Keywords
Field
DocType
Finite impulse response (FIR),Inter-symbol interference (ISI),Unit interval (UI),Equalization,Serializer–deserializer (SerDes),Decision feedback equalizer (DFE),Switched capacitor (SC)
Serial communication,Wireline,Equalization (audio),Communication channel,Electronic engineering,Switched capacitor,Bandwidth (signal processing),Test case,Attenuation,Mathematics
Journal
Volume
Issue
ISSN
36
12
0278-081X
Citations 
PageRank 
References 
0
0.34
4
Authors
2
Name
Order
Citations
PageRank
Jacob, N.A.101.35
Bibhudatta Sahoo29126.57