Name
Abstract | ||
|---|---|---|
Most existing computer architecture simulators are cycle oriented, i.e., they are driven cycle by cycle. However, frequent switches among simulation contexts, excessive buffer accesses and tightly coupled manner often make such an architecture simulator slow, difficult to parallelize and hard to scale to large-scale many-core systems. In this paper, we propose Prophet, a parallel instruction-orien... |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/TPDS.2017.2700307 | IEEE Transactions on Parallel and Distributed Systems |
Keywords | Field | DocType |
Computational modeling,Timing,Data models,Pipelines,Registers,Clocks | Data modeling,Computer architecture simulator,Cache,Computer science,Xeon Phi,Real-time computing,Instructions per second,Multi-core processor,Distributed computing,Shared memory,Simulation,Word error rate,Parallel computing | Journal |
Volume | Issue | ISSN |
28 | 10 | 1045-9219 |
Citations | PageRank | References |
3 | 0.39 | 20 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Weihua Zhang | 1 | 174 | 30.34 |
| ji xiaofeng | 2 | 9 | 2.07 |
| Yunping Lu | 3 | 12 | 1.89 |
| Haojun Wang | 4 | 5 | 1.44 |
| Haibo Chen | 5 | 1749 | 123.40 |
| P.-C. Yew | 6 | 199 | 25.56 |