Name
Abstract | ||
|---|---|---|
Memory fences are widely used to ensure the correctness for synchronization constructs on machines with relaxed consistency models. However, they are expensive and usually impose over-constrained ordering that causes unnecessary CPU stalls. In this paper, we observe that memory fences in TSO are merely intended to order synchronization variables. Based on this observation, we rethink the hardware-... |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/TPDS.2016.2633353 | IEEE Transactions on Parallel and Distributed Systems |
Keywords | Field | DocType |
Program processors,Synchronization,Buffer storage,Hardware,Load modeling,Algorithm design and analysis | Synchronization,Serialization,Computer science,Data synchronization,Parallel computing,Compiler,Real-time computing,Consistency model,Concurrent data structure,Synchronization (computer science),Multi-core processor,Distributed computing | Journal |
Volume | Issue | ISSN |
28 | 12 | 1045-9219 |
Citations | PageRank | References |
0 | 0.34 | 20 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yang Hong | 1 | 124 | 35.87 |
| yang zheng | 2 | 35 | 8.53 |
| Haibing Guan | 3 | 1106 | 105.35 |
| Binyu Zang | 4 | 984 | 62.75 |
| Haibo Chen | 5 | 1749 | 123.40 |