Name
Abstract | ||
|---|---|---|
Multi-Level Cell Phase Change Memory (MLC PCM) is a promising candidate technology for DRAM replacement in main memory of modern computers. Despite of its high density and low power advantages, this technology seriously suffers from slow read and write operations. While prior works extensively studied the problem of slow write, this paper targets high read latency problem in MLC PCM and introduces... |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/TPDS.2017.2705125 | IEEE Transactions on Parallel and Distributed Systems |
Keywords | Field | DocType |
Phase change materials,Resistance,Random access memory,Prefetching,Memory management,Microprocessors | Registered memory,Semiconductor memory,Interleaved memory,Uniform memory access,Computer science,Real-time computing,Memory map,Computer hardware,Memory architecture,Memory controller,Memory refresh | Journal |
Volume | Issue | ISSN |
28 | 11 | 1045-9219 |
Citations | PageRank | References |
2 | 0.37 | 22 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mohammad Arjomand | 1 | 273 | 20.31 |
| Amin Jadidi | 2 | 77 | 5.45 |
| Mahmut T. Kandemir | 3 | 7371 | 568.54 |
| Anand Sivasubramaniam | 4 | 4485 | 291.86 |
| Chita R. Das | 5 | 1046 | 45.21 |