Name
Abstract | ||
|---|---|---|
The authors target the typical problem of a small number of test access ports. As a solution, they propose a set of interposers to obtain access to the tested nets. Jörg Henkel, Karlsruhe Institute of Technology |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/MDAT.2015.2471296 | IEEE Design & Test |
Keywords | Field | DocType |
Circuit faults,Testing,Circuit synthesis,Wires,Three-dimensional displays,Through-silicon vias,Stacking | Test synthesis,Computer science,Silicon interposer,Electronic engineering,Interposer,Electrical engineering,Silicon,Stacking | Journal |
Volume | Issue | ISSN |
34 | 6 | 2168-2356 |
Citations | PageRank | References |
0 | 0.34 | 1 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Katherine Shu-Min Li | 1 | 133 | 29.02 |
| Sying-Jyan Wang | 2 | 306 | 42.06 |
| Ruei-Ting Gu | 3 | 4 | 1.59 |
| Bo-Chuan Cheng | 4 | 3 | 2.45 |