Name
Title | ||
|---|---|---|
Application of Scanning Capacitance Microscopy on SOI device with wafer edge low yield pattern. |
Abstract | ||
|---|---|---|
As semiconductor technology keeps scaling down, many advanced technology and process were applied in the semiconductor process. Especially for the application of IOT (internet of thing) technology, the low leakage and low power consumption product was the key component for this kind of application. SOI (Silicon-On-Insulator) wafer process is one of the advanced and important branches of the semiconductor manufacturing process. Its intrinsic advantage, low leakage and lower power consuming make it very suitable for personal communication device and IOT which match well with the application requirement. As is well known the SOI wafer is different form the normal bulk silicon wafer. The active sits on the silicon oxide insulator, which makes the final device separate from the substrate. Basically, all of the devices are floating on a nonconductive oxide layer. It comes with many challenges for process and analysis as compared with the conventional bulk silicon process. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1016/j.microrel.2017.07.014 | Microelectronics Reliability |
Keywords | Field | DocType |
SOI,SCM,Nanoprobing,Capacitance,Low yield | Nanoprobing,Silicon on insulator,Wafer,Capacitance,Leakage (electronics),Semiconductor device fabrication,Scanning capacitance microscopy,Electronic engineering,Engineering,Insulator (electricity) | Journal |
Volume | ISSN | Citations |
76 | 0026-2714 | 0 |
PageRank | References | Authors |
0.34 | 1 | 9 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| C. Q. Chen | 1 | 0 | 2.37 |
| G. B. Ang | 2 | 1 | 1.98 |
| P. T. Ng | 3 | 0 | 0.68 |
| Francis Rivai | 4 | 0 | 1.01 |
| S. P. Neo | 5 | 0 | 0.34 |
| D. Nagalingam | 6 | 0 | 0.34 |
| K. H. Yip | 7 | 0 | 0.34 |
| Jeffery Lam | 8 | 0 | 0.68 |
| Z. H. Mai | 9 | 1 | 4.34 |