Title
A 1.4×FO4 self-clocked asynchronous serial link in 0.18 µm for intrachip communication.
Abstract
In this paper, we describe a repeater-free asynchronous serial link architecture targeting 1×FO4 bit time for on-chip communication. Non-Return To Zero (NRZ) Data/Strobe code is used in the channel to achieve the target speed. Timing pulse trains are generated locally and are employed to drive high speed ‘transition latches’ in the serializer and deserializer. A RLC line model is derived by the HFSS electromagnetic solver. Inverter-based transmitters and receivers are found to perform faster than other circuits. A prototype device having 30 links and fabricated in Tower Semiconductor 0.18μm CMOS process is described. Measurement results show 3.73Gb/s data rate over 6.1mm wire interconnect, corresponding to 1.44×FO4 bit time.
Year
DOI
Venue
2017
10.1016/j.vlsi.2017.06.007
Integration
Keywords
DocType
Volume
On-chip interconnect,Serial links,Current-mode receiver,Asynchronous circuits
Journal
59
Issue
ISSN
Citations 
C
0167-9260
1
PageRank 
References 
Authors
0.36
11
7
Name
Order
Citations
PageRank
Y. Zhang112.72
Rostislav (Reuven) Dobkin225317.78
Aharon Unikovski310.36
Danniel Nahmanny410.36
G. Samuel571.24
Michael Moyal6201.25
ran ginosar7688.38