Paper Info
Title
A 12-bit 4928 × 3264 pixel CMOS image signal processor for digital still cameras.
Abstract
In this paper a 4928 × 3264 pixel CMOS image signal processor (ISP) is proposed for digital still cameras with low complexity and high performance. To reduce hardware cost and keep high performance, novel algorithms are proposed to process image signals. Firstly, a joint demosaic and denoise algorithm is presented for both color interpolation and Gaussian noise removal. This novel joint algorithm achieves high performance and saves line buffers. Furthermore, image edge enhancement is performed jointly with this algorithm to save memory cost. Secondly, a low complexity auto white balance hardware architecture is presented based on histogram equalization algorithm. This algorithm can handle some extremely bad scenes. To reduce hardware cost, the contrast enhancement is realized jointly with auto white balance. Thirdly, to remove pulse noise, a high performance and low complexity hardware implementation is proposed based on median filter using only nine comparators. Based on these algorithms and hardware, the VLSI architecture of the ISP is proposed and implemented in a SMIC 65nm CMOS technology. The gate count of the ISP is 158k and core area is 1.5mm2. Only 8 line buffers with total 462 Kb SRAM are used in the ISP. The throughput of the ISP is 12Gb/s with a frequency of 333MHz and power consumption of 77mW.
Year
DOI
Venue
2017
10.1016/j.vlsi.2017.06.005
Integration
Keywords
Field
DocType
Bayer image format,Digital still camera (DSC),Image signal processor (ISP),VLSI implementation
Gate count,Median filter,Computer science,Demosaicing,Electronic engineering,Color balance,Real-time computing,Histogram equalization,Gaussian noise,Edge enhancement,Hardware architecture
Journal
Volume
Issue
ISSN
59
C
0167-9260
Citations 
PageRank 
References 
1
0.35
16
Authors
4
Name
Order
Citations
PageRank
Wei Jin18325.25
Guanghui He28012.73
Weifeng He36114.69
Zhigang Mao419941.73