Name
Abstract | ||
|---|---|---|
The aim of the hierarchical cache memories that are equipped for GPUs is the management of irregular memory access patterns for general purpose workloads. The level-1 data cache (L1D) of the GPU plays an important role for its ability in the provision of high bandwidth and low-latency data accesses. Unfortunately, the GPU L1D may become a performance bottleneck due to facing many performance challenges such as cache contention and resource congestion. These critical issues come from a large number of simultaneous requests from the SIMT cores to the limited-capacity L1D. We observe that many applications have a large number of requests with a very low reuse probability, resulting in the GPU performance degradation. To overcome these challenges, we propose an efficient cache bypassing mechanism that can periodically filter the access stream and make an accurate bypassing decision to improve the efficiency of the L1D. The proposed technique uses a small storage amount to save the tag array of the L1D for the early miss prediction before it makes the bypassing decision. The experiment results reveal that the proposed technique significantly increases the cache efficiency and the GPU performance. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1016/j.micpro.2017.09.007 | Microprocessors and Microsystems |
Keywords | Field | DocType |
GPGPU,Cache,Bypass,Performance | Cache-oblivious algorithm,Cache invalidation,Cache pollution,Cache,Computer science,Parallel computing,Cache algorithms,Real-time computing,Page cache,Cache coloring,Smart Cache | Journal |
Volume | Issue | ISSN |
55 | C | 0141-9331 |
Citations | PageRank | References |
0 | 0.34 | 39 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| cong thuan do | 1 | 4 | 1.77 |
| Jong Myon Kim | 2 | 144 | 32.36 |
| Cheol Hong Kim | 3 | 73 | 24.39 |