Name
Abstract | ||
|---|---|---|
A parallel decimal multiplier with improved performance is proposed in this paper by exploiting the properties of three different binary coded decimal (BCD) codes, namely the redundant BCD excess-3 code (XS-3), the overloaded decimal digit set (ODDS) code and the BCD-4221/5211 code. The signed-digit radix-10 recoding is used to recode the BCD multiplier to the digit set [-5, 5] from [0, 9]. The re... |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/TC.2017.2706262 | IEEE Transactions on Computers |
Keywords | Field | DocType |
Adders,Encoding,Arithmetic,Algorithm design and analysis | Adder,Computer science,Parallel computing,Arithmetic,Algorithm,Multiplication,Excess-3,Binary Integer Decimal,Decimal floating point,Decimal,Binary-coded decimal,Binary number | Journal |
Volume | Issue | ISSN |
66 | 12 | 0018-9340 |
Citations | PageRank | References |
1 | 0.39 | 17 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xiao-Ping Cui | 1 | 8 | 2.27 |
| Wenwen Dong | 2 | 1 | 0.39 |
| weiqiang liu | 3 | 135 | 28.76 |
| Earl E. Swartzlander, Jr. | 4 | 946 | 181.88 |
| Fabrizio Lombardi | 5 | 57 | 10.81 |