Name
Abstract | ||
|---|---|---|
AbstractTypical radio frequency (RF) digital beamformers can be highly complex. In addition to a suitable antenna array, they require numerous receiver chains, demodulators, data converter arrays, and digital signal processors. To recover and reconstruct the received signal, synchronization is required since the analog-to-digital converters (ADCs), digital-to-analog converters (DACs), field programmable gate arrays (FPGAs), and local oscillators are all clocked at different frequencies. In this article, we present a clock synchronization topology for a multichannel on-site coding receiver (OSCR) using the FPGA as a master clock to drive all RF blocks. This approach reduces synchronization errors by a factor of 8, when compared to conventional digital beamformer. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1155/2017/7802735 | Periodicals |
Field | DocType | Volume |
Master clock,Synchronization,Digital signal processor,Computer science,Field-programmable gate array,Antenna array,Real-time computing,Clock synchronization,Digital clock manager,Self-clocking signal | Journal | 2017 |
Issue | ISSN | Citations |
1 | 1687-7195 | 0 |
PageRank | References | Authors |
0.34 | 1 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Satheesh Bojja Venkatakrishnan | 1 | 4 | 2.38 |
| Elias A. Alwan | 2 | 5 | 3.20 |
| Volakis, J.L. | 3 | 15 | 7.17 |