Name
Title | ||
|---|---|---|
Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience). |
Abstract | ||
|---|---|---|
We present cross-layer exploration for architecting resilience, a first of its kind framework which overcomes a major challenge in the design of digital systems that are resilient to reliability failures: achieve desired resilience targets at minimal costs (energy, power, execution time, and area) by combining resilience techniques across various layers of the system stack (circuit, logic, archite... |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/TCAD.2017.2752705 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | DocType | Volume |
Resilience,Flip-flops,Benchmark testing,Computer architecture,Integrated circuit reliability,Reliability engineering | Journal | 37 |
Issue | ISSN | Citations |
9 | 0278-0070 | 3 |
PageRank | References | Authors |
0.40 | 0 | 11 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Eric Cheng | 1 | 16 | 2.97 |
| Shahrzad Mirkhani | 2 | 127 | 9.56 |
| Lukasz G. Szafaryn | 3 | 141 | 7.69 |
| Chen-Yong Cher | 4 | 770 | 39.92 |
| Hyungmin Cho | 5 | 413 | 22.09 |
| Kevin Skadron | 6 | 6188 | 384.18 |
| Mircea R. Stan | 7 | 3103 | 277.34 |
| klas lilja | 8 | 13 | 2.02 |
| J. Abraham | 9 | 4905 | 608.16 |
| Pradip Bose | 10 | 2790 | 210.58 |
| Subhasish Mitra | 11 | 3657 | 228.90 |