Title
Para2: parameterized path reduction, acceleration, and SMT for reachability in threshold-guarded distributed algorithms.
Abstract
Automatic verification of threshold-based fault-tolerant distributed algorithms (FTDA) is challenging: FTDAs have multiple parameters that are restricted by arithmetic conditions, the number of processes and faults is parameterized, and the algorithm code is parameterized due to conditions counting the number of received messages. Recently, we introduced a technique that first applies data and counter abstraction and then runs bounded model checking (BMC). Given an FTDA, our technique computes an upper bound on the diameter of the system. This makes BMC complete for reachability properties: it always finds a counterexample, if there is an actual error. To verify state-of-the-art FTDAs, further improvement is needed. In contrast to encoding bounded executions of a counter system over an abstract finite domain in SAT, in this paper, we encode bounded executions over integer counters in SMT. In addition, we introduce a new form of reduction that exploits acceleration and the structure of the FTDAs. This aggressively prunes the execution space to be explored by the solver. In this way, we verified safety of seven FTDAs that were out of reach before.
Year
DOI
Venue
2017
https://doi.org/10.1007/s10703-017-0297-4
Formal Methods in System Design
Keywords
DocType
Volume
Parameterized verification,Bounded model checking,Completeness,Partial orders in distributed systems,Reduction,Fault-tolerant distributed algorithms,Byzantine faults
Journal
51
Issue
Citations 
PageRank 
2
0
0.34
References 
Authors
0
4
Name
Order
Citations
PageRank
Igor Konnov15712.06
Marijana Lazic203.04
Helmut Veith32476140.58
Josef Widder422923.99