Name
Abstract | ||
|---|---|---|
Series structures are inevitable and common in the design of digital logic gates. In this paper, to reduce the leakage power, we transplant the technique of mixed forward and reverse back-gate bias (mixed FBB/RBB) from FinFET forced stacks to the more widely-used series structures in FinFET logic gates. By employing the mixed FBB/RBB technique, the goal of leakage reduction is achieved without speed penalty. Performance of series structures of NMOS/PMOS transistors are studied. Simulation results based on the Predictive Technology Model 32nm FinFET model indicate that the speed can be maintained the same while reducing the leakage up to a factor of 18.3 compared with the structure without mixed back-gate biasing. This approach provides us a new viewpoint in designing low stand-by circuits without any sacrifice in the speed. The 16-bit ripple carry adder based on this methodology can acquire at least 51.8% leakage reduction. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/ASICON.2015.7517049 | PROCEEDINGS OF 2015 IEEE 11TH INTERNATIONAL CONFERENCE ON ASIC (ASICON) |
Keywords | Field | DocType |
Back-Gate Biasing, FinFET, Series Structure, Leakage | Logic gate,NMOS logic,Pass transistor logic,Adder,Leakage (electronics),Computer science,Electronic engineering,Real-time computing,Electronic circuit,PMOS logic,Transistor,Electrical engineering | Conference |
ISSN | Citations | PageRank |
2162-7541 | 0 | 0.34 |
References | Authors | |
0 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wang Tian | 1 | 17 | 15.16 |
| Xiaoxin Cui | 2 | 35 | 6.59 |
| Liao Kai | 3 | 5 | 2.09 |
| Nan Liao | 4 | 35 | 4.56 |
| Ni Yewen | 5 | 6 | 1.88 |
| Dunshan Yu | 6 | 44 | 12.56 |
| Cui Xiaole | 7 | 21 | 15.35 |