Name
Abstract | ||
|---|---|---|
Current-steering CMOS digital-to-analog converters (DACs) are widely used ultrahigh-speed systems. However, two main testability problems arise with sampling rates above tens of gigabits: the difficulty of generating input digital testing patterns at gigabit data rates, and the restricted analog output bandwidth due to the parasitic capacitance. To overcome above difficulties, the paper presents two auxiliary design schemes. One is on-chip register-based memory for providing high input digital data rates above Gb/s, and the other is the output bandwidth enhancement technique with passive inductors. Two chips are designed employing the presented schemes. The measurement results of 6.4GS/s DAC prototype show the auxiliary on-chip memory can generate parallel gigabit data properly. The post-layout simulation results of 20GS/s DAC indicate the presented bandwidth extension scheme achieves >12GHz -3dB bandwidth, nearly 50% bandwidth improvement. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/ASICON.2017.8252405 | 2017 IEEE 12th International Conference on ASIC (ASICON) |
Keywords | Field | DocType |
auxiliary testability design schemes,current-steering CMOS digital-to-analog converters,ultrahigh-speed systems,auxiliary on-chip memory,on-chip register-based memory,analog output bandwidth,CMOS DAC | Testability,Gigabit,Parasitic capacitance,Computer science,Bandwidth extension,Inductor,CMOS,Converters,Electronic engineering,Bandwidth (signal processing) | Conference |
ISSN | ISBN | Citations |
2162-7541 | 978-1-5090-6626-1 | 0 |
PageRank | References | Authors |
0.34 | 0 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Bao Li | 1 | 185 | 38.33 |
| Long Zhao | 2 | 0 | 4.06 |
| Yu-Hua Cheng | 3 | 2 | 5.85 |