Name
Abstract | ||
|---|---|---|
LU decomposition is widely used in the field of numerical analysis and engineering to solve large-scale sparse linear equations. The complex data dependency makes it difficult to parallelize the LU decomposition. In this paper, an architecture with an efficient cache for parallel sparse LU decomposition using FPGA is proposed. The proposed architecture is based on the Gilbert-Peierls (G-P) algorithm. By using the elimination graph, we find the column dependency of the LU decomposition. It is thus possible to exploit the parallelism. Through a dependency table, a simple but efficient cache strategy and its corresponding architecture are proposed. The proposed cache strategy avoids the cache miss and reduces the size of cache used to store all the intermediate data on chip. The experiment demonstrates that, our design can achieve speedup of 2.85x-10.27x, compared with UMFPACK running on general purpose processors. The cache size can be reduced by 50.93% on average with the proposed cache strategy. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/ASICON.2017.8252462 | 2017 IEEE 12th International Conference on ASIC (ASICON) |
Keywords | Field | DocType |
parallel sparse LU decomposition,FPGA,efficient cache architecture,numerical analysis,large-scale sparse linear equations,complex data dependency,parallelism,cache strategy,cache miss,cache size,Gilbert-Peierls algorithm,G-P,UMFPACK,general purpose processors,elimination graph,column dependency | Algorithm design,Computer science,CPU cache,Cache,Parallel computing,Matrix decomposition,Cache-only memory architecture,Real-time computing,LU decomposition,Sparse matrix,Speedup | Conference |
ISSN | ISBN | Citations |
2162-7541 | 978-1-5090-6626-1 | 0 |
PageRank | References | Authors |
0.34 | 0 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xiang Ge | 1 | 1 | 0.71 |
| Hengliang Zhu | 2 | 85 | 13.49 |
| Fan Yang | 3 | 101 | 22.74 |
| Lingli Wang | 4 | 45 | 7.03 |
| Xuan Zeng | 5 | 408 | 75.96 |