Paper Info
Title
Handling of transient and permanent faults in dynamically scheduled super-scalar processors.
Abstract
This article describes architectural extensions for a dynamically scheduled processor to enable three different operation modes, ranging from high-performance, to high-reliability. With minor extensions of the control path, the resources of the super-scalar data-path can be used either for high-performance execution, fail-safe-operation, or fault-tolerant-operation. Furthermore, the online error-correction capabilities are combined with reconfiguration techniques for permanent fault handling. This reconfiguration can take defective components out of operation permanently, and can be triggered on-demand during runtime, depending on the frequency of online corrected faults. A comprehensive fault simulation was carried out in order to evaluate hardware overhead, fault coverage and performance penalties of the proposed approach. Moreover, the impact of the permanent reconfiguration regarding the reliability and performance is investigated.
Year
DOI
Venue
2018
10.1016/j.microrel.2017.11.021
Microelectronics Reliability
Keywords
Field
DocType
Fault tolerance,Fail-safe,Dynamically scheduled processor
Scalar processor,Fault coverage,Fault handling,Ranging,Engineering,Reliability engineering,Control reconfiguration,Embedded system
Journal
Volume
ISSN
Citations 
80
0026-2714
0
PageRank 
References 
Authors
0.34
10
3
Name
Order
Citations
PageRank
Felix Mühlbauer1224.36
Lukas Schröder200.34
Mario Schölzel34211.27