Name
Abstract | ||
|---|---|---|
In deeply scaled CMOS technologies, device aging causes transistor performance parameters to degrade over time. While reliable models to accurately assess these degradations are available for devices and circuits, the extension to these models for estimating the aging of microprocessor cores is not trivial and there is no well accepted model in the literature. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1016/j.microrel.2017.07.067 | Microelectronics Reliability |
Keywords | Field | DocType |
Reliability,NBTI aging,Embedded processors,Modeling,Simulation,System-level models | Netlist,Upper and lower bounds,Aging effect,Microprocessor,Electronic engineering,CMOS,Engineering,Transistor,Electronic circuit | Journal |
Volume | ISSN | Citations |
80 | 0026-2714 | 0 |
PageRank | References | Authors |
0.34 | 14 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yukai Chen | 1 | 17 | 6.98 |
| Enrico Macii | 2 | 2405 | 349.96 |
| Massimo Poncino | 3 | 460 | 57.48 |