Name
Title | ||
|---|---|---|
A Scheme to Improve the Intrinsic Error Detection of the Instruction Set Architecture. |
Abstract | ||
|---|---|---|
The Instruction Set Architecture (ISA) determines the effect that a soft error on an instruction can have on the processor. Previous works have shown that the ISA has some intrinsic capability of detecting errors. For example, errors that change a valid instruction into an invalid instruction encoding or into an instruction that causes an exception. The percentage of detectable errors varies widel... |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/LCA.2016.2623628 | IEEE Computer Architecture Letters |
Keywords | Field | DocType |
Encoding,Circuit faults,Error analysis,Instruction sets,Computer architecture | ARM architecture,Opcode,Soft error,Instruction set,Computer science,Parallel computing,Error detection and correction,Real-time computing,Encoder,Decoding methods,Encoding (memory) | Journal |
Volume | Issue | ISSN |
16 | 2 | 1556-6056 |
Citations | PageRank | References |
4 | 0.49 | 8 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jorge A. Martinez | 1 | 10 | 2.64 |
| Juan Antonio Maestro | 2 | 439 | 51.17 |
| Pedro Reviriego | 3 | 527 | 75.56 |