Name
Title | ||
|---|---|---|
An 84.6-dB-SNDR and 98.2-dB-SFDR Residue-Integrated SAR ADC for Low-Power Sensor Applications. |
Abstract | ||
|---|---|---|
This paper presents an asynchronous-clocking successive approximation register (SAR) analog-to-digital converter (ADC) suitable for ultralow-power fine-precision sensor applications whose signal bandwidth is in the kilohertz range. The performance-limiting issues of comparator noise and capacitor mismatch in SAR ADC are resolved by a residue integration scheme combined with a dynamic element match... |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/JSSC.2017.2774287 | IEEE Journal of Solid-State Circuits |
Keywords | Field | DocType |
Capacitors,Registers,Power demand,Capacitance,Noise shaping,Linearity,Switches | Dynamic range,Comparator,Computer science,Signal-to-noise ratio,Spurious-free dynamic range,Electronic engineering,Figure of merit,Noise shaping,Successive approximation ADC,Amplifier | Journal |
Volume | Issue | ISSN |
53 | 2 | 0018-9200 |
Citations | PageRank | References |
1 | 0.35 | 0 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Seungnam Choi | 1 | 17 | 3.57 |
| Hwan-Seok Ku | 2 | 1 | 0.35 |
| Hyunwoo Son | 3 | 11 | 4.43 |
| Byungsub Kim | 4 | 165 | 37.71 |
| Hong-june Park | 5 | 465 | 72.93 |
| Jae-yoon Sim | 6 | 508 | 83.58 |