Name
Abstract | ||
|---|---|---|
This paper presents a solution to address verification-related challenges during the design and validation for motor control applications that call for joint simulation of the control algorithm and the motor. One method used previously involved playback of a prerecorded motor response in order to get around a lack of an HDL model for the motor, resulting in erroneous results. To circumvent this, we present a workflow approach using FPGA-in-the-Loop simulation (FIL), which configures an FPGA with the HDL design and uses it as a computation block for closed-loop simulation. The approach is illustrated to implement, test, and validate two control schemes: a vector based Field Oriented Control (FOC) and the scalar voltage by frequency (V/f) algorithms on a permanent magnet synchronous machine. The proposed approach is useful to provide validation before hardware implementation. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/RECONFIG.2017.8279774 | 2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig) |
Keywords | Field | DocType |
FPGA,FPGA-in-the-Loop (FIL),Motor Control Verification,Field Oriented Control (FOC) | Vector control,Induction motor,Synchronous motor,Computer science,Field-programmable gate array,Real-time computing,Motor control,DC motor,Motor controller,Control system,Computer hardware | Conference |
ISSN | ISBN | Citations |
2325-6532 | 978-1-5386-3798-2 | 0 |
PageRank | References | Authors |
0.34 | 4 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Paul Rogers | 1 | 0 | 0.34 |
| Rajesh G. Kavasseri | 2 | 31 | 6.98 |
| Scott C. Smith | 3 | 129 | 18.15 |