Title
Towards a type 0 hypervisor for dynamic reconfigurable systems
Abstract
The usage of application-specific hardware based on Field-Programmable Gate Arrays (FPGA) has proven its benefits. Current system-on-chips, which contain FPGA fabric, supporting dynamic partial reconfiguration, enable a dynamic hardware acceleration for hardware/software co-designs. With the trend to consolidate multiple computing systems into a single system, applications with mixed criticalities can come into conflict. With our approach, we are exploring the possibility to utilize dedicated hardware for the system management and benefit from possible parallelization of applications and system management tasks.
Year
DOI
Venue
2017
10.1109/RECONFIG.2017.8279825
2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig)
Keywords
Field
DocType
FPGA,Zynq,Hypervisor,Virtualitzation,Microkernel,Mixed-Critical,Dynamic Partial Reconfiguration
Computer science,Field-programmable gate array,Hypervisor,Real-time computing,Software,Memory management,Hardware acceleration,Systems management,Control reconfiguration,Computing systems,Embedded system
Conference
ISSN
ISBN
Citations 
2325-6532
978-1-5386-3798-2
0
PageRank 
References 
Authors
0.34
0
6
Name
Order
Citations
PageRank
Benedikt Janßen1133.51
Fatih Korkmaz200.34
Halil Derya300.34
Hubner, Michael439047.98
Mário Ferreira581.96
João Canas Ferreira67216.69