Name
Abstract | ||
|---|---|---|
Linearizability is the standard correctness notion for concurrent objects, i.e., objects designed to be accessed simultaneously by multiple threads. In this paper, we explain why the original definition of linearizability is not applicable to code running on the weak memory models supported by modern multicore architectures, and provide an alternative definition which is applicable. In contrast to earlier work, our definition is proved to be both sound and complete. Furthermore, while earlier work has focussed on linearizability for the TSO (Total Store Order) architecture, ours is applicable to any existing weak memory model. We illustrate how it can be used to prove the correctness of a simple case study on the widely used TSO, Power and ARM architectures. |
Year | Venue | Field |
|---|---|---|
2018 | arXiv: Logic in Computer Science | Linearizability,ARM architecture,Architecture,Parallel computing,Correctness,Algorithm,Thread (computing),Total store order,Memory model,Multi-core processor,Mathematics |
DocType | Volume | Citations |
Journal | abs/1802.04954 | 0 |
PageRank | References | Authors |
0.34 | 12 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Graeme Smith | 1 | 348 | 34.02 |
| Kirsten Winter | 2 | 13 | 2.06 |
| Robert Colvin | 3 | 68 | 8.67 |