Name
Abstract | ||
|---|---|---|
The IBM Z microprocessor in the z14 system has been redesigned to improve performance, system capacity, and security [1] over the previous z13 system [2]. The system contains up to 24 central processor (CP) and 4 system controller (SC) chips. Each CP, shown in die photo A (Fig. 2.2.7), operates at 5.2GHz and is comprised of 10 cores, 2 PCIe Gen3 interfaces, an IO bus controller (GX), 128MB of L3 embedded DRAM (eDRAM) cache, X-BUS interfaces connecting to 2 other CP chips and one SC chip, and a redundant array of independent memory (RAIM) interface. Each core on the CP chip has 4MB of eDRAM L2 Data cache and 2MB of eDRAM L2 Instruction cache, with 128KB SRAM Instruction and 128KB SRAM Data L1 caches. Each SC, shown in die photo B (Fig. 2.2.7), operates at 2.6GHz and has 672MB of L4 eDRAM cache, X-BUS interfaces connecting to CP chips in the drawer and A-BUS interfaces connecting SCs on the other drawers. Both chips are 696mm
<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>
and are designed in Global Foundries 14nm high performance (14HP) SOI FinFET technology with 17 layers of copper interconnect [3]. The CP contains 6.1B transistors, while the SC contains 9.7B transistors. The total IO bandwidth of the CP and SC are 2.9Tb/s and 5.5Tb/s, respectively. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/ISSCC.2018.8310171 | 2018 IEEE International Solid - State Circuits Conference - (ISSCC) |
Keywords | Field | DocType |
14nm microprocessor,next-generation mainframe,IBM Z microprocessor,system capacity,die photo,IO bus controller,L3 embedded DRAM cache,X-BUS interfaces,CP chip,SC chip,independent memory interface,eDRAM L2 Data cache,eDRAM L2 Instruction cache,128KB SRAM Instruction,128KB SRAM Data L1 caches,L4 eDRAM cache,A-BUS interfaces,central processor,PCIe Gen3 interfaces,IBM z14,system controller chips,Global Foundries 14nm high performance SOI FinFET technology,size 14.0 nm,frequency 5.2 GHz,memory size 128.0 MByte,memory size 4.0 MByte,memory size 128.0 KByte,frequency 2.6 GHz,memory size 672.0 MByte,size 696.0 mm,memory size 2.0 MByte | Dram,Cache,Computer science,Microprocessor,Static random-access memory,eDRAM,PCI Express,Electrical engineering,Redundant array of independent memory,Embedded system,Control bus | Conference |
ISBN | Citations | PageRank |
978-1-5386-2227-8 | 2 | 0.44 |
References | Authors | |
0 | 25 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Christopher J. Berry | 1 | 20 | 3.84 |
| James D. Warnock | 2 | 54 | 6.47 |
| John Isakson | 3 | 15 | 3.01 |
| John Badar | 4 | 13 | 2.29 |
| Brian Bell | 5 | 28 | 4.52 |
| Frank Malgioglio | 6 | 44 | 5.43 |
| G. Mayer | 7 | 40 | 5.26 |
| Dina Hamid | 8 | 7 | 1.95 |
| Jesse Surprise | 9 | 7 | 1.95 |
| David H. Wolpert | 10 | 4334 | 591.07 |
| ofer geva | 11 | 7 | 2.63 |
| Bill Huott | 12 | 92 | 11.82 |
| Leon J. Sigal | 13 | 39 | 6.61 |
| Sean M. Carey | 14 | 76 | 15.11 |
| Richard F. Rizzolo | 15 | 32 | 4.64 |
| Ricardo Nigaglioni | 16 | 22 | 2.95 |
| Mark Cichanowski | 17 | 12 | 2.57 |
| Dureseti Chidambarrao | 18 | 4 | 1.17 |
| Christian Jacobi | 19 | 177 | 17.22 |
| Anthony Saporito | 20 | 15 | 4.18 |
| Arthur O'neill | 21 | 3 | 0.79 |
| Robert Sonnelitter | 22 | 2 | 0.44 |
| Christian G. Zoellin | 23 | 134 | 9.31 |
| Michael Wood | 24 | 16 | 2.98 |
| José Neves | 25 | 6 | 0.96 |