Name
Title | ||
|---|---|---|
Hardware Implementation of an Image Interpolation Method with Controllable Sharpness. |
Abstract | ||
|---|---|---|
The technique of image scaling plays a critical role in the digital image processing applications for the coordination between different display devices. In this paper, an improved algorithm is proposed by using a controllable sharpness coefficient to obtain better resulting images under different scaling magnifications. In addition, a power saving module including a condition judgment mechanism is applied to reduce unnecessary power consumption as the scaling ratio increases. Experimental results show that the proposed architecture is still feasible for very large-scale integration implementation and effectively enhances the quality of image scaling. By using TSMC 0.13 mu m cell library, the synthesis results show that the circuit can achieve 300 MHz with 12.1k gate counts and cell area is 293x293 mu m(2). The total power consumption is 6.75mW. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.6688/JISE.2018.34.1.4 | JOURNAL OF INFORMATION SCIENCE AND ENGINEERING |
Keywords | Field | DocType |
controllable sharpness,image scaling,interpolation,low-power design,VLSI | Computer science,Computational science,Image scaling,Distributed computing | Journal |
Volume | Issue | ISSN |
34 | 1 | 1016-2364 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pei-Yin Chen | 1 | 314 | 38.47 |
| Shih-Hsiang Lin | 2 | 5 | 1.25 |
| Po-Chun Chen | 3 | 0 | 0.34 |