Name
Abstract | ||
|---|---|---|
This article presents an approach that helps convert a given C program into a hardware implementation for a digital circuit design. Based on and extended from the concept of hierarchical finite-state machines (HFSMs), four built-in HFSM templates, namely Seq, Par, Loop and Atomic, are proposed and used as the elementary components of a hardware design. A guideline on the refinement of a C program is also proposed; the refined C functions are compiled into HFSMs that in turn generate synthesizable hardware description language (HDL) code as the final design. A set of HFSMs is viewed as an intermediate representation between C and HDL and can be functionally simulated. Two modeling levels, i.e. cycle-accurate and cycle-approximated, are supported. A compilation technique based on syntax-directed translations is used to automate the proposed approach. Experimental results on several well-known algorithmic benchmarks show the effectiveness of the proposed approach. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.6688/JISE.2018.34.2.2 | JOURNAL OF INFORMATION SCIENCE AND ENGINEERING |
Keywords | Field | DocType |
finite state machine,intermediate representation,hardware synthesis,hardware description language | Computer architecture,Hardware circuits,Computer science,Distributed computing | Journal |
Volume | Issue | ISSN |
34 | 2 | 1016-2364 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Cheng-Juei Yu | 1 | 1 | 1.04 |
| Yi-Hsin Wu | 2 | 0 | 0.34 |
| Sheng-De Wang | 3 | 720 | 68.13 |